View STV7610A_5965683.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. version 4.7 august 2003 adcs 7155031 1/14 STV7610A plasma display panel data driver features n 96 output- plasma display driver n 100 v absolute maximum rating n 5 v supply for logic n -70/+90 ma source/sink output mos n 6 bit cascadable data bus (20 mhz) n blank, polarity control n bcd technology n packaging tqfp144 or dic description the STV7610A is a bcd data driver for plasma display panel (pdp). using a 6-bit wide cascada- ble data bus, it addresses 96 high current & high voltage outputs. by serially connecting several STV7610A, any horizontal pixel definition can be performed. the 20 mhz shift clock gives an equiv- alent 120 mhz shift register. the STV7610A is supplied with a separated 90 v power output sup- ply and a 5 v logic supply. all command inputs are cmos compatible. die order code : STV7610A/waf(1) (1): unsawn tested wafer 1
table of contents 2 2/14 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ac timings requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 ac timings characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 input/output schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 tested wafer disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2
STV7610A adcs 7155031 3/14 pin connections (die pinout) v pp out33 out32 out31 out30 out29 out28 out27 out26 out25 out24 out23 out22 out21 out20 out19 out18 out17 out16 out15 out14 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out96 out95 out94 out93 out92 out91 out90 out89 out88 out87 out86 out85 out84 out83 out82 out81 out80 out79 out78 out77 out76 out75 out74 out73 out72 out71 out70 out69 out68 out67 out66 out65 out64 v pp out63 out62 out61 out60 out59 out58 out57 out56 out55 out54 out53 out52 out51 out50 out49 out48 out47 out46 out45 out44 out43 out42 out41 out40 out39 out38 out37 out36 out35 out34 v ssp v ssp v ssp v pp b6 b5 b4 b3 b2 b1 blk f/r pol v cc v sslog v sssub clk stb a1 a2 a3 a4 a5 a6 v pp v ssp STV7610A bare die v pp v pp (0,0) y x 3
STV7610A 4/14 adcs 7155031 pad coordinates (in m m) pad positions from the middle of the top side pad positions along the right side pad positions along the bottom side name center size xyxy out 48 74.0 3034.0 80.0 90.0 out 47 210.0 3034.0 80.0 90.0 out 46 346.0 3034.0 80.0 90.0 out 45 482.0 3034.0 80.0 90.0 out 44 618.0 3034.0 80.0 90.0 out 43 754.0 3034.0 80.0 90.0 out 42 890.0 3034.0 80.0 90.0 out 41 1026.0 3034.0 80.0 90.0 out 40 1162.0 3034.0 80.0 90.0 out 39 1298.0 3034.0 80.0 90.0 out 38 1434.0 3034.0 80.0 90.0 out 37 1570.0 3034.0 80.0 90.0 out 36 1706.0 3034.0 80.0 90.0 out 35 1842.0 3034.0 80.0 90.0 out 34 1993.0 3034.0 80.0 90.0 name centre size xyxy v ssp 2116.0 2795.0 90.0 80.0 v pp 2029.8 2496.5 90.0 90.0 v pp 2041.5 1843.0 90.0 80.0 out 33 2117.0 1580.0 90.0 80.0 out 32 2117.0 1444.0 90.0 80.0 out 31 2117.0 1308.0 90.0 80.0 out 30 2117.0 1172.0 90.0 80.0 out 29 2117.0 1036.0 90.0 80.0 out 28 2117.0 900.0 90.0 80.0 out 27 2117.0 764.0 90.0 80.0 out 26 2117.0 628.0 90.0 80.0 out 25 2117.0 492.0 90.0 80.0 out 24 2117.0 356.0 90.0 80.0 out 23 2117.0 220.0 90.0 80.0 out 22 2117.0 84.0 90.0 80.0 out 21 2117.0 -52.0 90.0 80.0 out 20 2117.0 -188.0 90.0 80.0 out 19 2117.0 -324.0 90.0 80.0 out 18 2117.0 -460.0 90.0 80.0 out 17 2117.0 -596.0 90.0 80.0 out 16 2117.0 -732.0 90.0 80.0 out 15 2117.0 -868.0 90.0 80.0 out 14 2117.0 -1004.0 90.0 80.0 out 13 2117.0 -1140.0 90.0 80.0 out 12 2117.0 -1276.0 90.0 80.0 out 11 2117.0 -1412.0 90.0 80.0 out 10 2117.0 -1548.0 90.0 80.0 out 9 2117.0 -1684.0 90.0 80.0 out 8 2117.0 -1820.0 90.0 80.0 out 7 2117.0 -1956.0 90.0 80.0 out 6 2117.0 -2092.0 90.0 80.0 out 5 2117.0 -2228.0 90.0 80.0 out 4 2117.0 -2364.0 90.0 80.0 out 3 2117.0 -2500.0 90.0 80.0 out 2 2117.0 -2636.0 90.0 80.0 out 1 2117.0 -2832.0 90.0 80.0 name centre size xyxy v ssp 1904.0 -3034.0 80.0 90.0 v pp 1698.0 -3034.0 80.0 90.0 a6 1499.0 -3034.0 80.0 90.0 a5 1349.0 -3034.0 80.0 90.0 a4 1199.0 -3034.0 80.0 90.0 a3 1049.0 -3034.0 80.0 90.0 a2 899.0 -3034.0 80.0 90.0 a1 749.0 -3034.0 80.0 90.0 stb 449.0 -3034.0 80.0 90.0 clk 299.0 -3034.0 80.0 90.0 gndsub 156.5 -3034.0 80.0 90.0 name centre size xyxy 3
STV7610A adcs 7155031 5/14 pad positions along the left side pad positions along the top side gnd 3.0 -3034.0 80.0 90.0 v cc -158.0 -3034.0 80.0 90.0 f/r -299.0 -3034.0 80.0 90.0 pol -449.0 -3034.0 80.0 90.0 blk -599.0 -3034.0 80.0 90.0 b1 -749.0 -3034.0 80.0 90.0 b2 -899.0 -3034.0 80.0 90.0 b3 -1049.0 -3034.0 80.0 90.0 b4 -1199.0 -3034.0 80.0 90.0 b5 -1349.0 -3034.0 80.0 90.0 b6 -1499.0 -3034.0 80.0 90.0 v pp -1698.0 -3034.0 80.0 90.0 v ssp -1904.0 -3034.0 80.0 90.0 name centre size xyxy out 96 -2117.0 -2832.0 90.0 80.0 out 95 -2117.0 -2636.0 90.0 80.0 out 94 -2117.0 -2500.0 90.0 80.0 out 93 -2117.0 -2364.0 90.0 80.0 out 92 -2117.0 -2228.0 90.0 80.0 out 91 -2117.0 -2092.0 90.0 80.0 out 90 -2117.0 -1956.0 90.0 80.0 out 89 -2117.0 -1820.0 90.0 80.0 out 88 -2117.0 -1684.0 90.0 80.0 out 87 -2117.0 -1548.0 90.0 80.0 out 86 -2117.0 -1412.0 90.0 80.0 out 85 -2117.0 -1276.0 90.0 80.0 out 84 -2117.0 -1140.0 90.0 80.0 out 83 -2117.0 -1004.0 90.0 80.0 out 82 -2117.0 -868.0 90.0 80.0 out 81 -2117.0 -732.0 90.0 80.0 out 80 -2117.0 -596.0 90.0 80.0 out 79 -2117.0 -460.0 90.0 80.0 out 78 -2117.0 -324.0 90.0 80.0 name centre size xyxy out 77 -2117.0 -188.0 90.0 80.0 out 76 -2117.0 -52.0 90.0 80.0 out 75 -2117.0 84.0 90.0 80.0 out 74 -2117.0 220.0 90.0 80.0 out 73 -2117.0 356.0 90.0 80.0 out 72 -2117.0 492.0 90.0 80.0 out 71 -2117.0 628.0 90.0 80.0 out 70 -2117.0 764.0 90.0 80.0 out 69 -2117.0 900.0 90.0 80.0 out 68 -2117.0 1036.0 90.0 80.0 out 67 -2117.0 1172.0 90.0 80.0 out 66 -2117.0 1308.0 90.0 80.0 out 65 -2117.0 1444.0 90.0 80.0 out 64 -2117.0 1580.0 90.0 80.0 v pp -2041.5 1843.0 90.0 80.0 v pp -2029.8 2496.5 90.0 80.0 v ssp -2116.0 2795.0 90.0 80.0 name centre size xyxy out 63 -1980.0 3034.0 80.0 90.0 out 62 -1830.0 3034.0 80.0 90.0 out 61 -1694.0 3034.0 80.0 90.0 out 60 -1558.0 3034.0 80.0 90.0 out 59 -1422.0 3034.0 80.0 90.0 out 58 -1286.0 3034.0 80.0 90.0 out 57 -1150.0 3034.0 80.0 90.0 out 56 -1014.0 3034.0 80.0 90.0 out 55 -878.0 3034.0 80.0 90.0 out 54 -742.0 3034.0 80.0 90.0 out 53 -606.0 3034.0 80.0 90.0 out 52 -470.0 3034.0 80.0 90.0 out 51 -334.0 3034.0 80.0 90.0 out 50 -198.0 3034.0 80.0 90.0 out 49 -62.0 3034.0 80.0 90.0 name centre size xyxy 3
STV7610A 6/14 adcs 7155031 block diagram logic 16-bit shift register p1 p91 16-bit shift register p2 p92 16-bit shift register 16-bit shift register p4 p94 16-bit shift register p5 p95 16-bit shift register p6 p96 latch q1 q96 p3 p93 q2 q95 p96 p95 p6 p1 52 53 56 59 49 60 48 61 47 62 46 63 45 64 44 57 54 55 50 51 73 36 v ssp pins 40-68-109-144 v pp pins 1-2-42-66-107-108 v cc v sssub v sslog b6 b5 b4 b3 b2 b1 a1 a2 a3 a4 a5 a6 stb pol blk for/rev clk out1 out96 STV7610A v cc v cc v cc 3
STV7610A adcs 7155031 7/14 circuit description the STV7610A contains all the logic and the pow- er circuits necessary to drive the columns of a plasma display panel (p. d. p.). the binary value of each pixel of the displayed line is loaded into the shift register. data are input in a 6-bit wide data bus to a1 - a6 input (case of forward shift mode). data are shifted at each low to high transition of the clk shift clock. after 16 shifts the first data are available on b1 - b6 outputs. these b1 - b6 out- puts can be used to cascade several drivers to perform any horizontal resolution. the forward/ (f/ r ) input is used to select the direc- tion of the shift register, a1 - a6 and b1 - b6 data bus input/output status is set according to the se- lected direction. f/ r = h, a is an input and b is an output. serial inputs, clk, stb inputs are smith trigger in- puts. if not used in the application, blanking ( blk ), polarity ( pol are internally pulled to level h. the maximum frequency of the shift clock is 20 mhz. this leads to an equivalent 120 mhz serial shift register. on low level of stb, data is transferred from shift register to the latch stage. data will not be re- freshed as long as stb is kept high. blanking input ( blk ) forces the power outputs to low level when pulled low. all the power outputs are set at high level when the polarity command ( pol ) is pulled low and the blanking ( blk ) input is at high level. v sssub and v sslog must be connected as close as possible to the logical reference ground of the application. shift register truth table power output truth table note 1 qn+1 = a1, qn + 2 = a2, qn + 3 = a3, qn + 4 = a4, qn + 5 = a5, qn + 6 = a6, n = [0,6,12,18,...,90] reverse input input/output shift register function f/r clk a b output q h rise in out forward shift h h or l in out steady l rise out in reverse shift l h or l out in steady qn stb blk pol driver output comments x x l x l output low x x h l h output high x h h h qn data latched l l h h l data copied h l h h h data copied 3
STV7610A 8/14 adcs 7155031 absolute maximum ratings note 2 through one power output (all power outputs). note 3 through one power output for all power outputs (see test diagram) with junction temperature lower or equal than t j max. note 4 these parameters are measured during sts internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. these parameters are not tested on the parts. note 5 transient current. spike current duration inferior to 300ns. symbol parameter value unit v cc logic supply range (pin 53) -0.3, +7 v outi output pins (4 to 36, 73 to 105, 112 to 141) -0.3, +100 v v in logic input voltage (pins 50, 51, 52, 56, 57, 59 to 64) -0.3, +v cc +0.3 v v out logic output voltage (pin 44 to 49) -0.3, +v cc + 0.3 v i pout driver output current ( note 2 ) ( note 4 ) ( note 5 ) -150/ +150 ma i dout diode output current ( note 3 ) ( note 4 ) ( note 5 ) -200/ +300 ma t j junction temperature +150 c t oper operating temperature -20, +85 c t stg storage temperature -50, +150 c 3
STV7610A adcs 7155031 9/14 electrical characteristics (v cc = 5 v, v pp = 90 v, v ssp = 0 v, v sslog = 0 v, v sssub = 0 v, t amb = 25c, f clk = 20 mhz, unless otherwise specified) symbol parameter test conditions min. typ. max. unit supply v cc logic supply voltage 4.5 5 5.5 v i cch logic supply current (all inputs high) - - 100 a i ccl logic dynamic supply current f clk = 20 mhz - 26 - ma v pp power output supply voltage 15 - 90 v i pph power output supply current (steady outputs) --100a output (v pp = 15 v to 90 v) out 1- out 96 v pouth power output voltage drop (high level) (versus v pp ) i pouth = - 30 ma i pouth = - 45ma - - 4.0 4.5 6.0 6.5 v v v poutl power output voltage drop (low level) i poutl = + 30 ma - 1.6 4 v v douth output diode voltage (high level) i douth = +45 ma ( figure 2 ) - 1.05 4 v v doutl output diode low level i doutl = - 30ma ( figure 2 ) - -0.95 -4 v a1-a6, b1-b6 v oh logic output (high level) i oh = -1 ma 4 4.2 - v v ol logic output (low level) i ol = +1 ma - 0.12 0.4 v input clk, f/r , stb, pol , blk , a1-a6, b1-b6 v ih input voltage (high level) 0.8 v cc --v v il input voltage (low level) - - 0.2v cc v i ih high level input current v ih = v cc --10a i il low level input current clk, a1-a6, b1-b6, stb, f/r , blk , pol v il = 0 v - - - - -10 -40 a a 3
STV7610A 10/14 adcs 7155031 ac timings requirements (v cc = 4.5 v to 5.5 v, t amb = -20 to +85c, input signals max leading edge & trailing edge (t r , t f ) = 10 ns) ac timings characteristics (v cc = 5 v, v pp = 90 v , v spp = 0 v, v sslog = 0 v, v sssub = 0 v, t amb = 25c) (v il(max.) = 0.2 vcc, v ih(min.) =0.8 v cc , v oh = 4.0v, v ol = 0.4 v, unless otherwise specified) note 6 for ic in cascading configuration and in case a time delay is inserted on the clock signal of the cascaded ic, the maximum value of this time delay must be set at the minimum value of t phl1, t plh1 ( figure 7 ). note 7 one output among 96, loading capacitor c l = 50pf, other outputs at low level. symbol parameter min. typ. max. unit t whclk duration of clock (clk) pulse at high level 15 - - ns t wlclk duration of clock (clk) pulse at low level 15 - - ns t sdat set-up time of data input before clock (low to high) transition 10 - - ns t hdat hold time of data input after clock (low to high) transition 10 - - ns t sfr forward/ (f/r ) set-up time before clock (low to high) transition 100 - - ns t dstb minimum delay to latch stb after clock (low to high) transition 10 - - ns t sstb minimum delay to latch stb before clock (low to high) transition 10 - - ns t stb latch stb low level pulse duration 20 - - ns t blk blanking blk pulse duration 500 - - ns t pol polarity pol pulse duration 500 - - ns symbol parameter min. typ. max. unit t clk data clock period 50 - - ns t rdat logical data output rise time (cl=10pf) - 12 20 ns t fdat logical data output fall time (cl=10pf) - 11 20 ns t phl1 t plh1 delay of logic data output (high to low transition) after clock (clk) transition note 6 delay of logic data output (low to high transition) after clock (clk) transition note 6 15 15 35 35 50 50 ns ns t phl2 t plh2 delay of power output change (high to low transition) after clock (clk) transition delay of power output change (low to high transition) after clock (clk) transition - - 135 80 180 180 ns ns t phl3 t plh3 delay of power output change (high to low transition) after latch (stb) transition delay of power output change (low to high transition) after latch (stb) transition - - 115 70 165 165 ns ns t phl4 t plh4 delay of power output change (high to low transition) to blank or polarity (blk ,pol ) transition delay of power output change (low to high transition) to blank or polarity (blk ,pol ) transition - - 100 55 160 160 ns ns t rout power output rise time ( note 7 ) - 50 150 ns t fout power output fall time ( note 7 ) - 80 200 ns reverse 3
STV7610A adcs 7155031 11/14 figure 1: ac characteristics waveform f/r outn outn blk (pol =#0#) t sfr 1 0 t phl3 t plh3 90% 10% t phl2 t plh2 1 0 t blk 50% 50% 1 0 90% 10% 1 0 t phl4 t plh4 90% 10% t r out t f out 90% 10% stb 50% 50% t stb t sstb 0 1 t hstb t clk t whclk t wlclk 0 1 clk 0 1 t sdat t hdat 50% 50% a input 0 1 10% 90% 90% 10% t phl1 t plh1 t fdat t rdat b output 3
STV7610A 12/14 adcs 7155031 figure 2: test configuration input/output schematics figure 3: pol , blk , f/ r input figure 4: clk, stb input figure 5: a1 to a6, b1 to b6 figure 6: power output v douth i douth v ssp v doutl i doutl v ssp v pp = v ssp v pp = v ssp output sinking current as positive value, sourcing current as negative value pol, blk, f/r pins 51, 50, 52 v cc v cc gndlog gndsub clk, stb pins 56, 57 v cc v cc gndlog gndsub a1 to a6, b1 to b6 pins 59 to 64, 49 to 44 v cc v cc gndlog gndsub v cc v pp out1 to out 96 pins 73 to 105, 112 to 141, 4 to 3 6 v ssp 3
STV7610A adcs 7155031 13/14 figure 7: ic cascading mode suggestion tested wafer disclaimer all wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for a period of ninety (90) days from the delivery date. we remind you that it is the customers responsibility to test and qualify their application in which the die is used. st microelectronics is ready to support the customer when qualifying the product. STV7610A STV7610A time delay data in data out data in clock vcc 3
STV7610A 14/14 adcs 7155031 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel -italy - japan - malaysia - malta-morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 4

▲Up To Search▲

Price & Availability of STV7610A

	To Download STV7610A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .